Interrupt

Because there was only a single interrupt line on the I/O bus, the occurrence of an interrupt did not inform the processor of the source of the interrupt.

Difficulty with sharing interrupt lines Multiple devices sharing an interrupt line (of any triggering style) all act as spurious interrupt sources with respect to each other.

Edge-triggered An edge-triggered interrupt is an interrupt signalled by a level transition on the interrupt line, either a falling edge (high to low) or a rising edge (low to high).

For interrupts, a program called an interrupt handler is installed, and it is the interrupt handler that handles the interrupt from the disk.

More modern hardware often has one or more interrupt status registers that latch the interrupt requests; well written edge-driven interrupt software often checks such registers to ensure events are not missed.

That is, a higher-numbered interrupt can always interrupt a lower-numbered interrupt.

Upon detecting assertion of the interrupt line, the CPU must search through the devices sharing the interrupt request line until one who triggered the interrupt is detected.

Accordingly, interrupt latency is increased by however long that interrupt is blocked.

A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input.

A device wishing to signal a Level-triggered interrupt drives the interrupt request line to its active level (high or low), and then holds it at that level until it is serviced.

As stated above, a device was expected to raise its "done" I/O flag when it requested an interrupt, and the convention was that the device would clear its interrupt request when the CPU executed a I/O clear instruction on the device's channel number.

But if the function is used in a reentrant interrupt handler and a second interrupt arises inside the function, the second routine will hang forever.

Devices signal an interrupt by briefly driving the line to its non-default state, and let the line float (do not actively drive it) when not signalling an interrupt.

Each interrupt has its own interrupt handler.

If there is a device that the CPU does not know how to service, it may cause a spurious interrupt, or even periodic spurious interrupts, but it does not interfere with the interrupt signalling of the other devices.

Instead of stacking the PC and CC registers (normal 6809 behavior) the FIRQ interrupt can be set to stack the entire register set, as the IRQ interrupt does.

Interrupt latency In contrast to general-purpose computers, microcontrollers used in embedded systems often seek to optimize interrupt latency over instruction throughput.

Interrupts and interrupt handling From the hardware standpoint, the interrupt mechanism was relatively simple, but also less flexible, than current CPU architectures.

Maximum interrupt latency is largely determined by the methods an OS uses for interrupt handling.

Minimum interrupt latency is largely determined by the interrupt controller circuit and its configuration.