Explore Pipelining through 10+ example sentences from English, with an explanation of the meaning. Ideal for language learners, writers and word enthusiasts.
Pipelining meaning
present participle and gerund of pipeline
Using Pipelining
- The main meaning on this page is: present participle and gerund of pipeline
Context around Pipelining
- Average sentence length in these examples: 27.3 words
- Position in the sentence: 7 start, 3 middle, 1 end
- Sentence types: 11 statements, 0 questions, 0 exclamations
Corpus analysis for Pipelining
- In this selection, "pipelining" usually appears near the start of the sentence. The average example has 27.3 words, and this corpus slice is mostly made up of statements.
- Around the word, deep, super, simple, mathematical, sequences and uses stand out and add context to how "pipelining" is used.
- Recognizable usage signals include as instruction pipelining in which and both simple pipelining and superscalar. That gives this page its own corpus information beyond isolated example sentences.
- By corpus frequency, "pipelining" sits close to words such as aami, aat and abada, which helps place it inside the broader word index.
Example types with pipelining
The same corpus examples are grouped by length and sentence type, making it easier to see the contexts in which the word appears:
The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). (18 words)
Pipelining as a basic technique was well known before (see IBM 801 for instance), but not developed into its full potential. (21 words)
Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages. (22 words)
Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains. (35 words)
In order to reduce the amount of time consumed by these steps, most modern CPUs use a technique known as instruction pipelining in which the instructions pass through several sub-units in turn. (33 words)
Due to the tight pipelining, sequences of simple instructions (such as ALU reg,reg and ALU reg,im) could sustain a single clock cycle throughput (one instruction completed every clock). (30 words)
Example sentences (11)
The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time).
Both simple pipelining and superscalar design increase a CPU's ILP by allowing a single processor to complete execution of instructions at rates surpassing one instruction per clock cycle.
By highly pipelining mathematical instructions with purpose-built instructions and hardware, mathematical processing is dramatically improved in a machine that was otherwise slower than a 7600.
Due to the tight pipelining, sequences of simple instructions (such as ALU reg,reg and ALU reg,im) could sustain a single clock cycle throughput (one instruction completed every clock).
In computers, pipelining uses separate circuits to work on different parts of different instructions at the same time, in a fashion similar to the many stations on an assembly line.
In order to reduce the amount of time consumed by these steps, most modern CPUs use a technique known as instruction pipelining in which the instructions pass through several sub-units in turn.
Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages.
Pipelining as a basic technique was well known before (see IBM 801 for instance), but not developed into its full potential.
Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict.
Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains.
The performance can be improved by executing different substeps of sequential instructions simultaneously (termed pipelining), or even executing multiple instructions entirely simultaneously as in superscalar architectures.