Pipelined

A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications.

If the 68060's non-pipelined FPU could accept an instruction, it could be issued one by the decoder.

In a traditional non-optimized design, a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution; in a pipelined architecture, successive instructions can instead overlap in execution.

Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.

Many of these games required the speed of the P5 Pentium processor family's double-pipelined architecture.

Naturally, accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones (though not very significantly so).

The Cray-1 had twelve pipelined functional units.

The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache.

The Westinghouse radar used a pipelined fast fourier transform (FFT) to digitally resolve 128 Doppler frequencies, while Hughes's radars used analog filters based on the design for the F-15 fighter.

This allowed a batch of vector instructions themselves to be pipelined, a technique they called vector chaining.