Pipelining

The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time).

Both simple pipelining and superscalar design increase a CPU's ILP by allowing a single processor to complete execution of instructions at rates surpassing one instruction per clock cycle.

By highly pipelining mathematical instructions with purpose-built instructions and hardware, mathematical processing is dramatically improved in a machine that was otherwise slower than a 7600.

Due to the tight pipelining, sequences of simple instructions (such as ALU reg,reg and ALU reg,im) could sustain a single clock cycle throughput (one instruction completed every clock).

HTTP pipelining further reduces lag time, allowing clients to send multiple requests before waiting for each response.

In computers, pipelining uses separate circuits to work on different parts of different instructions at the same time, in a fashion similar to the many stations on an assembly line.

In order to reduce the amount of time consumed by these steps, most modern CPUs use a technique known as instruction pipelining in which the instructions pass through several sub-units in turn.

Pipelining allows more than one instruction to be executed at any given time by breaking down the execution pathway into discrete stages.

Pipelining as a basic technique was well known before (see IBM 801 for instance), but not developed into its full potential.

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict.

Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous ALUs in conjunction with superscalar pipelining to achieve some arithmetic performance gains.

The performance can be improved by executing different substeps of sequential instructions simultaneously (termed pipelining), or even executing multiple instructions entirely simultaneously as in superscalar architectures.